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PRELIMINARY Integrated Circuit Systems, Inc. ICS843011C FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR FEATURES * One differential 3.3V LVPECL output * Crystal oscillator interface designed for 26.5625MHz 18pF parallel resonant crystal * Output frequency: 106.25MHz or 100MHz * VCO range: 560MHz - 680MHz * RMS phase jitter @ 100MHz, using a 25MHz crystal (637kHz - 10MHz): 0.29ps (typical) * 3.3V operating supply * -40C to 85C ambient operating temperature * Available in both standard and lead-free RoHS compliant packages GENERAL DESCRIPTION The ICS843011C is a Fibre Channel Clock Generator and a member of the HiPerClocksTM HiPerClockSTM family of high performance devices from ICS. The ICS843011C uses a 26.5625MHz crystal to synthesize 106.25MHz or a 25MHz crystal to synthesize 100MHz. The ICS843011C has excellent <1ps phase jitter performance, over the 637kHz - 10MHz integration range. The ICS843011C is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space. IC S FREQUENCY TABLE Crystal (MHz) 26.5625 25 Output Frequency (MHz) 106.25 100 BLOCK DIAGRAM XTAL_IN PIN ASSIGNMENT Phase Detector VCO 637.5MHz w/ 26.5625MHz Ref. OSC XTAL_OUT /6 Q nQ VCCA VEE XTAL_OUT XTAL_IN 1 2 3 4 8 7 6 5 VCC Q nQ nc M = /24 (fixed) ICS843011C 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 843011CG www.icst.com/products/hiperclocks.html REV. A JANUARY 25, 2006 1 PRELIMINARY Integrated Circuit Systems, Inc. ICS843011C FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR Type Power Power Input Description Analog supply pin. Negative supply pin. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. No connect. Differential clock outputs. LVPECL interface levels. Core supply pin. TABLE 1. PIN DESCRIPTIONS Number 1 2 3, 4 5 6, 7 8 Name VCCA VEE XTAL_OUT, XTAL_IN nc nQ, Q VCC Unused Output Power TABLE 2. PIN CHARACTERISTICS Symbol CIN Parameter Input Capacitance Test Conditions Minimum Typical 4 Maximum Units pF 843011CG www.icst.com/products/hiperclocks.html 2 REV. A JANUARY 25, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS843011C FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR 4.6V -0.5V to VCC + 0.5V 50mA 100mA 101.7C/W (0 mps) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V5%, TA = -40C TO 85C Symbol VCC VCCA ICCA IEE Parameter Core Supply Voltage Analog Supply Voltage Analog Supply Current Power Supply Current included in IEE Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 10 68 Maximum 3.465 3.465 Units V V mA mA TABLE 3B. LVPECL DC CHARACTERISTICS, VCC = 3.3V5%, TA = -40C TO 85C Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCC - 1.4 VCC - 2.0 0.6 Typical Maximum VCC - 0.9 VCC - 1.7 1.0 Units V V V NOTE 1: Outputs terminated with 50 to VCC - 2V. TABLE 4. CRYSTAL CHARACTERISTICS Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance 25 Test Conditions Minimum Typical Fundamental 26.5625 50 7 MHz pF Maximum Units TABLE 5. AC CHARACTERISTICS, VCC = 3.3V5%, TA = -40C TO 85C Symbol Parameter FOUT tjit(O) t R / tF odc Output Frequency RMS Phase Jitter (Random); NOTE 1 Output Rise/Fall Time Output Duty Cycle 106.25MHz; Integration Range: 637kHz - 10MHz 100MHz; Integration Range: 637kHz - 10MHz 20% to 80% Test Conditions Minimum 93.33 0.29 0.29 400 50 Typical Maximum 113.33 Units MHz ps ps ps % NOTE 1: Please refer to the Phase Noise Plot. 843011CG www.icst.com/products/hiperclocks.html 3 REV. A JANUARY 25, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS843011C FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION 2V Phase Noise Plot Noise Power VCC Qx SCOPE LVPECL nQx Phase Noise Mask VEE f1 Offset Frequency f2 -1.3V 0.165V RMS Jitter = Area Under the Masked Phase Noise Plot 3.3V OUTPUT LOAD AC TEST CIRCUIT RMS PHASE JITTER nQ Q t PW t PERIOD 80% Clock Outputs x 100% 80% VSW I N G 20% tR tF 20% odc = t PW t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD OUTPUT RISE/FALL TIME 843011CG www.icst.com/products/hiperclocks.html 4 REV. A JANUARY 25, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS843011C FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843011C provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V CC and V CCA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin. 3.3V VCC .01F 10 V CCA .01F 10F FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE The ICS843011C has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 26.5625MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. XTAL_OUT C1 33p X1 18pF Parallel Crystal XTAL_IN C2 22p Figure 2. CRYSTAL INPUt INTERFACE 843011CG www.icst.com/products/hiperclocks.html 5 REV. A JANUARY 25, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS843011C FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR generating 106.25MHz output frequency. The C1 = 27pF and C2 = 33pF are recommended for frequency accuracy. For different board layout, the C1 and C2 values may be slightly adjusted for optimizing frequency accuracy. APPLICATION SCHEMATIC Figure 3A shows a schematic example of the ICS843011C. An example of LVEPCL termination is shown in this schematic. Additional LVPECL termination approaches are shown in the LVPECL Termination Application Note. In this example, an 18 pF parallel resonant 26.5625MHz crystal is used for VCC R2 10 VCCA VCC C3 10uF C4 0.1u U2 Q XTAL_OUT 1 2 3 4 VCCA VEE XTAL_OUT XTAL_IN 843011C C5 0.1u R4 82.5 R6 82.5 VCC Q nQ nc 8 7 6 5 VCC + Zo = 50 Ohm R3 133 R5 133 Zo = 50 Ohm nQ C2 33pF X1 26.5625MHz 18pF - XTAL_IN C1 27pF Zo = 50 Ohm Q + Zo = 50 Ohm nQ R5 50 R6 50 Optional Y-Termination R7 50 FIGURE 3A. ICS843011C SCHEMATIC EXAMPLE PC BOARD LAYOUT EXAMPLE Figure 3B shows an example of ICS843011C P.C. board layout. The crystal X1 footprint shown in this example allows installation of either surface mount HC49S or through-hole HC49 package. The footprints of other components in this example are listed in the Table 6. There should be at least one decoupling capacitor per power pin. The decoupling capacitors should be located as close as possible to the power pins. The layout assumes that the board has clean analog power ground plane. TABLE 6. FOOTPRINT TABLE Reference C1, C2 C3 C4, C5 Size 0402 0805 0603 R2 0603 NOTE: Table 6, lists component sizes shown in this layout example. FIGURE 3B. ICS843011 PC BOARD LAYOUT EXAMPLE 843011CG www.icst.com/products/hiperclocks.html 6 REV. A JANUARY 25, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS843011C FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS843011C. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843011C is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * * Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 68mA = 235.6mW Power (outputs)MAX = 30mW/Loaded Output pair Total Power_MAX (3.465V, with all outputs switching) = 235.6mW + 30mW = 265.6mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.266W * 90.5C/W = 109.1C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 7. THERMAL RESISTANCE JA FOR 8-PIN TSSOP, FORCED CONVECTION JA by Velocity (Meters per Second) 0 Multi-Layer PCB, JEDEC Standard Test Boards 101.7C/W 1 90.5C/W 2.5 89.8C/W 843011CG www.icst.com/products/hiperclocks.html 7 REV. A JANUARY 25, 2006 PRELIMINARY Integrated Circuit Systems, Inc. 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 4. VCC ICS843011C FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR Q1 VOUT RL 50 VCC - 2V FIGURE 4. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V. CC * For logic high, VOUT = V (V CCO_MAX OH_MAX =V CC_MAX - 0.9V -V OH_MAX ) = 0.9V =V - 1.7V * For logic low, VOUT = V (V CCO_MAX OL_MAX CC_MAX -V OL_MAX ) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX - (V CC_MAX - 2V))/R ] * (V L CC_MAX -V OH_MAX ) = [(2V - (V CC_MAX -V OH_MAX ))/R ] * (V L CC_MAX -V OH_MAX )= [(2V - 0.9V)/50] * 0.9V = 19.8mW Pd_L = [(V OL_MAX - (V CC_MAX - 2V))/R ] * (V L CC_MAX -V OL_MAX ) = [(2V - (V CC_MAX -V OL_MAX ))/R ] * (V L CC_MAX -V OL_MAX )= [(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW 843011CG www.icst.com/products/hiperclocks.html 8 REV. A JANUARY 25, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS843011C FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR RELIABILITY INFORMATION TABLE 8. JAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP JA by Velocity (Meters per Second) 0 1 90.5C/W 2.5 89.8C/W Multi-Layer PCB, JEDEC Standard Test Boards 101.7C/W TRANSISTOR COUNT The transistor count for ICS843011C is: 2436 843011CG www.icst.com/products/hiperclocks.html 9 REV. A JANUARY 25, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS843011C FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR 8 LEAD TSSOP PACKAGE OUTLINE - G SUFFIX FOR TABLE 9. PACKAGE DIMENSIONS SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 2.90 6.40 BASIC 4.50 Millimeters Minimum 8 1.20 0.15 1.05 0.30 0.20 3.10 Maximum Reference Document: JEDEC Publication 95, MO-153 843011CG www.icst.com/products/hiperclocks.html 10 REV. A JANUARY 25, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS843011C FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR Marking 3011C 3011C TBD TBD Package 8 lead TSSOP 8 lead TSSOP 8 lead "Lead-Free" TSSOP 8 lead "Lead-Free" TSSOP Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C TABLE 10. ORDERING INFORMATION Part/Order Number ICS843011CG ICS843011CGT ICS843011CGLF ICS843011CGLFT NOTE: Par ts that are ordered with an "LF suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring ehigh reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843011CG www.icst.com/products/hiperclocks.html 11 REV. A JANUARY 25, 2006 |
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